Review on Implementation of a High Performance Multiplier Using HDL
In this paper, the authors present implementation of high performance multiplier using HDL. In that paper for implementing the multiplier uses both encoder and carry look-ahead adder. This paper use VHDL language. The paper implementing for simulation used two types of software: Xilinx ISE 9.2i target towards Spartan 3 FPGA, modelsim SE6.4. Paper is based on FPGA and VLSI. Carry look ahead are used for enhance the speed of operation. Radix-4 Booth multiplier with 3:2 compressors and Radix-8 Booth multiplier with 4:2 compressors are presented here.