International Journal of Engineering Associates
Advanced Encryption Standard (AES) and its recently standardized authentication Galois/Counter Mode (GCM) have been utilized in various security constrained applications. Many of the AESGCM applications are power and resource constrained and requires efficient hardware implementations. In this paper, different Application-Specific Integrated Circuit (ASIC) architectures of building blocks of the AESGCM algorithms are evaluated and optimized to identify the high-performance and low-power architectures for the AES-GCM. Security is one of the most important features in data communication. Cryptographic algorithms are mainly used for this purpose to obtain confidentiality and integrity of data in communication.