Routing Wire Optimization through Generic Synthesis on FPGA Carry Chains

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Provided by: Association for Computing Machinery
Topic: Hardware
Format: PDF
FPGA logic clusters are comprised of Look-Up Tables (LUTs) and arithmetic carry-chains, which perform specific arithmetic operations such as addition. In this paper, the authors present a generic logic synthesis technique to utilize such dedicated resources by restructuring the already mapped FPGA circuits. The basic idea is to replace the interconnection wires between the blocks that are logically in a chain by the carry chains, which are hardwired connections. This reduces the pressure on the routing resources and minimizes the utilization of routing wires.
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