RTL Desing and VLSI Implementation of an Efficient Convolution Encoder and Adaptive Viterbi Decoder
Error-correcting convolution codes provide a proven method to limit the effects of noise in digital data communication. Convolution codes are employed to implement Forward Error Correction (FEC) but the complexity of corresponding decoder's increases exponentially with the restraint length K. Sophistication encoding with Viterbi decoding is a powerful FEC technique that is particularly suited to a channel in which the transmitted signal is corrupted mainly by additive white Gaussian noise. Here, the authors present a convolution encoder and Viterbi decoder with a constraint length of 9 and code rate of 1/2. This is comprehended using Verilog HDL. It is simulated and synthesized using modalism Altera 10.0d and Xilinx 12.1 ISE.