RTL Verification of ARM SoC by JTAG

Provided by: AICIT
Topic: Hardware
Format: PDF
The design of SoC (System-on-Chip) based on ARM is becoming increasingly complex. Not only the area of chips increases, but also the simulation tests are becoming increasingly difficult. When in process of RTL (Register-Transfer Level) simulation, the SoC based on ARM debugging is completed by initializing the test programs in the ROM. A method of RTL verification by utilizing the JTAG debug interface of ARM is proposed. The JTAG standard and the ARM7TDMI scan chains are also analyzed in this paper. It gives the method to control the ARM7TDMI behavior. An ARM SoC based verification platform which can be used to verify ARM is designed. It can also control ARM to verify other IPs (Intellectual Property).

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