RTOS-Aware Refinement for TLM2.0-based HW/SW Designs
To manage the complexity of designs for refinement and synthesis, Gajski's Y-Chart was introduced several years ago. At that point in time, the Y-Chart was mainly applied for Register-Transfer and Gate Level synthesis. Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a tradeoff between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process.