Runtime 3-D Stacked Cache Management for Chip-Multiprocessors

Three-Dimensional (3-D) memory stacking is one of the most promising solutions to tackle memory bandwidth problems in chip multiprocessors. In this paper, the authors propose an efficient runtime 3-D cache management technique which not only takes advantage of the low memory access latency through vertical interconnections, but also exploits runtime memory access demand of applications which varies dynamically with time. Experimental results show that the proposed method offers performance improvement by up to 26.7% and on average 13.1% compared with a configuration of private stacked cache.

Provided by: Institute of Electrical & Electronic Engineers Topic: Hardware Date Added: Mar 2013 Format: PDF

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