Runtime Thermal Management for Three-Dimensional Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
Non-volatile memory such as Magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with SRAM. Three-Dimensional (3-D) integration technology using Through-Silicon Vias (TSVs) enables stacking disparate memory technologies (e.g., SRAM and MRAM) together onto Chip Multi-Processors (CMPs). The use of hybrid memories as an on-chip cache can take advantage of the best characteristics that each technology offers. However, the inherent high power density and heat removal limitation in 3-D integrated circuits may incur temperature-related problems.

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