Sankeerna: A Linear Time, Synthesis and Routing Aware, Constructive VLSI Placer to Achieve Synergistic Design Flow

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Provided by: International Journal of Advances in Engineering & Technology (IJAET)
Topic: Hardware
Format: PDF
Standard cell placement is a NP complete open problem. The main objectives of a placement algorithm are to minimize chip area and the total wire length of all the nets. Due to interconnect dominance, deep sub-micron VLSI design flow does not converge leading to iterations between synthesis and layout steps. The authors present a new heuristic placement algorithm called Sankeerna, which tightly couples synthesis and routing and produces compact routable designs with minimum area and delay.
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