Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory

In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true for a large-scale distributed memory system where multiple transactions may attempt to commit simultaneously and co-ordination is required before allowing commits to proceed in parallel. In this paper, the authors propose novel algorithms to implement commit that are more scalable and are free of deadlocks/livelocks. They show that these algorithms have similarities with the token cache coherence concept and leverage these similarities to extend the algorithms to handle message loss and starvation scenarios.