Scaling of Low Power CMOS Circuits with Optimum Performance
In recent years, increasing demand for portable devices has made low power consumption a main design consideration. This paper optimizes the CMOS basic cells based on a simulation procedure to analyze how three aspects of IC power consumption, i.e. dynamic power, leakage power and peak power, can be considered together in optimizing the sizing and design of basic cells without a reduced degradation in performance with scaled supply voltage. The study was performed using basic cells in 32nm process technology for 1.8V to sub-1V by exploiting the linear dependency of supply voltage VDD and width of transistor W with circuit switching delay and power consumption.