Institute of Electrical & Electronic Engineers
This paper is devoted to the design and the physical security of a parallel dual-core flexible crypto-processor for computing pairings over Barreto-Naehrig (BN) curves. The proposed design is specifically optimized for Field-Programmable Gate-Array (FPGA) platforms. The design explores the in-built features of an FPGA device for achieving an efficient crypto-processor for computing 128-bit secure pairings. The work further pinpoints the vulnerability of those pairing computations against side-channel attacks and demonstrates experimentally that power consumptions of such devices can be used to attack these ciphers. Finally, the authors suggest a suitable countermeasure to overcome the respective weaknesses.