Secure Information Flow for Concurrent Programs under Total Store Order

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Provided by: University of California, Irvine
Topic: Security
Format: PDF
Modern multicore hardware and multithreaded programming languages expose weak memory models to programmers, which relax the intuitive Sequential Consistency (SC) memory model in order to support a variety of hardware and compiler optimizations. However, to the authors' knowledge all prior work on secure information flow in a concurrent setting has assumed SC semantics. This paper investigates the impact of the Total Store Order (TSO) memory model, which is used by Intel x86 and Sun SPARC processors, on secure information flow, focusing on the natural security condition known as possibilistic noninterference.
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