Secure Public Verification of IP Marks in FPGA Using Modified LFSR

Provided by: International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Topic: Security
Format: PDF
Reuse of design or hardware components has become essential to meet shrinking time-to-market and more Integration on a single chip as per the customer's specifications at low cost. Circuit components in electronic form and hardware components are reused, and these constitute Intellectual Property (IP) core. In order to ensure trustworthy yet leakage-proof public verification based on the marks hidden in a FPGA design, this project presents a synchronized random key generation for each node which depends on the bit file information.

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