Provided by: Institute of Electrical & Electronic Engineers
Date Added: Jul 2006
In this paper, the authors propose a low-cost fault tolerance technique for microprocessor multipliers, both Non-Pipelined (NP) and Pipelined (P). Their fault tolerant multiplier de-signs are capable of detecting and correcting errors, diagnosing hard faults, and reconfiguring to take the faulty sub-unit off-line. They utilize the branch misprediction recovery mechanism in the microprocessor core to take the error detection process off the critical path. Their analysis shows that their scheme provides 99% fault security and, compared to a baseline unprotected multiplier, achieves this fault tolerance with low performance overhead (5% for NP and 2.5% for P multiplier) and reasonably low area (38% NP and 26% P) and power consumption (36% NP and 28.5% P) overheads.