Semiconductor Memory Testing Algorithm

Provided by: International Journal for Technological Research in Engineering (IJTRE)
Topic: Hardware
Format: PDF
In semi-conductor memories various faults occurs like stuck-at fault, coupling fault, pattern sensitive fault and bridging fault. This paper explains a test algorithm to detect faulty row present in the memory. In this testing memory an algorithm based on marching 1/0 is used. Xilinx ISE 9.1i is used for development of software algorithm. In this algorithm one test RAM is created with Verilog code which is instantiated in state machine. State machine will generate various data which is written to memory and read data from memory is also verified.

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