Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis

Provided by: Imperial College London
Topic: Hardware
Format: PDF
The capabilities of modern FPGAs permit the mapping of increasingly complex applications into reconfigurable hardware. High-Level Synthesis (HLS) promises a significant shortening of the FPGA design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. Applications using dynamic, pointer-based data structures and dynamic memory allocation, however, remain difficult to implement well, yet such constructs are widely used in software. Automated optimizations that aim to leverage the increased memory bandwidth of FPGAs by distributing the application data over separate banks of on-chip memory are often ineffective in the presence of dynamic data structures, due to the lack of an automated analysis of pointer-based memory accesses.

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