SHA-3 on ARM11 Processors

This paper presents high-speed assembly implementations of the 256-bit-output versions of all five SHA-3 finalists and of SHA-256 for the ARM11 family of processors. The authors report new speed records for all of the six implemented functions. For example, their implementation of the round-3 version of JH-256 is 35% faster than the fastest implementation of the round-2 version of JH-256 in eBASH. Scaled with the number of rounds this is more than a 45% improvement. They also improve upon previous assembly implementations for 32-bit ARM processors.

Provided by: National Taiwan University Topic: Data Centers Date Added: Nov 2011 Format: PDF

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