Shared Reconfigurable Architectures for CMPS

Provided by: Cornell University
Topic: Hardware
Format: PDF
In this paper, the authors investigate reconfigurable architectures suitable for Chip Multi-Processors (CMPs). Prior research has established that augmenting a conventional processor with reconfigurable logic can dramatically improve the performance of certain application classes, but this comes at nontrivial power and area costs. Given substantial observed time and space differences in fabric usage, they propose that pools of programmable logic should be shared among multiple cores. While a common shared pool is more compact and power efficient, fabric conflicts may lead to large performance losses relative to per-core private fabrics.

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