Side Channel Modeling Attacks on 65nm Arbiter PUFs Exploiting CMOS Device Noise

Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. For so-called strong PUFs, the number of Challenge-Response Pairs (CRPs) increases exponentially with the required chip area in the ideal case. They can provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. Modeling of the CRP behavior through Machine Learning (ML) has shown to be a threat however. In this paper, the authors exploit repeatability imperfections of PUF responses as a side channel for model building. They demonstrate that 65nm CMOS arbiter PUFs can be modeled successfully, without utilizing any ML algorithm.