Side-Channel Passive Attacks Implementation to Cryptographic Hardware Using FPGA

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Provided by: Creative Commons
Topic: Security
Format: PDF
In this paper, the authors dealt with an FPGA based test bed used for injecting faults through clock glitches, to result in setup and hold violations. The UART interface is realized on FPGA to provide PC based controlling for this fault injection. The pre-build serial International Data Encryption Algorithm (IDEA) algorithm synthesis models (.ngc files) will be used as test encryption algorithm. Their paper is to develop an efficient method for protecting FPGA-based implementations of cryptographic algorithms through effective concurrent testing of various types of faults, including faults injected by the attackers.
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