Signature-based SER Analysis and Design of Logic Circuits
In this paper, the authors explore the use of signatures, i.e., partial truth tables generated via bit-parallel functional simulation, during soft error analysis and logic synthesis. They first present a signature based CAD framework that incorporates tools for the logic-level Analysis of Soft Error Rate (AnSER) and for Signature-based Design for Reliability (SiDeR). They observe that the SER of a logic circuit is closely related to various testability parameters, such as signal observability and probability. They show that these parameters can be computed very efficiently (in linear time) by means of signatures.