Signed Pipelined Multiplier Using High Speed Compressors

Both unsigned and signed binary number operation instructions are essential in configurable Digital Signal Processors (DSPs) and special-purpose computers. In this paper, a unified implementation of signed/unsigned multiplication is proposed using a simple sign control unit together with a line of multiplexers. The proposed approach is demonstrated using CMOS implementation of a 32-bit signed/unsigned multiplier. The results show that the proposed unified signed/unsigned implementation is very compact with only 0.45% silicon area overhead. The critical path delay of the proposed multiplier is about 3.65 ns.

Provided by: Creative Commons Topic: Hardware Date Added: Sep 2013 Format: PDF

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