Provided by: International Journal of Emerging Technology and Advanced Engineering (IJETAE)
Date Added: Mar 2015
Power consumption and delay are two important considerations for VLSI systems which depend on various critical design parameters. This paper is to reduce the power and to reduce the delay which increases the speed. This paper is the design and implementation of an Arithmetic Logic Unit (ALU) using area optimizing techniques such as Gate Diffusion Input (GDI). In this paper, a high speed full adder simulated using improved GDI technique. The authors further implement it in 4-bit ALU by the concept of GDI technique.