Provided by: Bangladesh University of Engineering & Technology
In this paper, the authors focus on simulation and design of parameterized convolutional encoder and Viterbi decoder using coding rate, trellis length as parameter. In wireless communication high coding rate transmission is reliable but takes more time to decode comparing low coding rate. Long trellis length causes the Viterbi algorithm to take more time but reliable compare with short trellis length. These combined effects are taken as consideration for design and implementation. Using 1/2, 1/3 coding rate and 4, 15 trellis length four different convolutional encoder and Viterbi decoder is implemented using FPGA. Simulation is done using Quartus II 7.0.