Simulation and Synthesis of 32-Bit Multiplier Using Configurable Devices
Floating-point numbers are frequently used for numerical calculations in computing systems for better accuracy, but floating-point operations are complex and difficult to design on FPGAs. This paper attempts to design such hardware architecture for single precision floating-point multiplication that is easily implementable with high efficiency. The multiplier unit is based on ancient Vedic mathematics technique. The proposed design is described using VHDL which is simulated using ModelSim SE 5.7f and synthesized using ISE Xilinx 10.1i on FPGA device Virtex XC4VSX25-12FF668.