Provided by: International Journal of Computer Applications
Date Added: Jul 2011
In this paper, the authors present two new 1-bit full adder cells operating in subthreshold region with 65nm, 90nm and 0.18um technologies. Circuits designed in this region usually consume less power. Inverse Majority Gate (IMG) together with NAND/NOR were used as the main computational building blocks. A modification was done to optimize W/L ratios with different supply voltages. They used W/L ratios for all the PMOS transistors 1.5 times the ratio of W/L for all NMOS transistors.