Simulation of Convolutional Encoder and Viterbi Decoder Using Verilog
In this paper, the authors are implementing the convolutional encoder and viterbi decoder with code rate 2/3 using verilog. This paper is to implement the RTL level model of convolutional encoder and viterbi decoder, with the testing results of behavior model. They tried to achieve a low silicon cost. The viterbi algorithm, used for convolutional codes extensively employed decoding algorithm for convolutional codes. This paper is realized using verilog HDL. It is simulated and synthesized using modelsim Altera 10.1d.