Simulative Investigations of DDR2 (SDRAM) Model in HDL
With the increase of computer performance in recent years, the requirements of higher bandwidth and better memory performance are growing day-by-day. There is a frequent demand for computer memories to be faster, larger, lower powered and physically small. This paper presents a simulation based implementation of DDR2 memory model in HDL language. The paper covers single data rate, double data rate and their comparisons. This model consists of five blocks i.e. Instruction decoder, DDR2 interface, SRAM interface, bank control and adder reorder. This paper is evaluated using Xilinx 12.4 ISE and ISIM is used for simulation.