Single Dictionary based Cache Compression and Decompression Algorithm

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Provided by: International Journal of Innovative Technology and Exploring Engineering (IJITEE)
Topic: Storage
Format: PDF
Computer systems and micro architecture researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functionality. All work on cache compression, has made unsubstantiated assumptions about the performance, power consumption, and area overheads of the proposed compression algorithms and hardware. It is not possible to determine whether compression at levels of the memory hierarchy closest to the processor is beneficial without understanding its costs.
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