MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, almost all MCML circuits are realized with dual-rail scheme. The dual-rail logic circuits increase extra area overhead and the complexity of the layout place and route. Moreover, little standard cells of the dual-rail logic circuits have been developed for place-and-route tools, such as Cadence Encounter. In this paper, a single-rail scheme of MCML circuits is proposed. The design methods of the basic Single-Rail MOS Current-Mode Logic (SRMCML) circuits are presented, such as inverter/buffer, OR2/NOR2, AND2/NAND2, OR3/NOR3, and 1-bit full adder.