Six New Full Adder Cells Based on Majority-Not Gate in 45nm CMOS Technology and Analysis in SOI Technology
In this paper, the authors present six new 1-bit full adder topologies operating 45nm technology and SOI technology. Inverse Majority Gate (IMG) together with NAND/NOR were used as the main computational building blocks. Six new 1-bit full adder cells are simulated 45nm CMOS technology and SOI technology with different supply voltages using the conventional 1.5:1 for Wp/Wn. Simulation results are compared with a previously reported majority-not based full adder. The results involve better performance in terms of power, delay, and PDP.