Provided by: University of Calgary
Date Added: Nov 2009
Modern digital IC designs have a critical operating point, or \"Wall of slack\", that limits voltage scaling. Even with an error-tolerance mechanism, scaling voltage below a critical voltage - so-called overscaling - results in more timing errors than can be effectively detected or corrected. This limits the effectiveness of voltage scaling in trading off system reliability and power. The authors propose a design-level approach to trading off reliability and voltage (power) in, e.g., microprocessor designs. They increase the range of voltage values at which the (timing) error rate is acceptable; they achieve this through techniques for power-aware slack redistribution that shift the timing slack of frequently-exercised, near-critical timing paths in a power- and area-efficient manner.