Slew-Aware Buffer Insertion for Through-Silicon-Via-Based 3D ICs

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Provided by: Institute of Electrical and Electronics Engineers
Topic: Hardware
Format: PDF
For high performance 3D ICs, it is crucial to perform thorough timing optimization, especially when the 3D nets are on timing critical paths. Large parasitic capacitances of through-silicon vias in 3D ICs cause signal slew and delay to increase. The authors propose a buffer insertion algorithm that further reduces delay by considering slew explicitly. Compared with the well-known van Ginneken algorithm and a commercial 2D tool, their algorithm improves full-chip timing with acceptable runtime overhead.
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