SMTp: An Architecture for Next-Generation Scalable Multi-Threading

Provided by: Cornell University
Topic: Hardware
Format: PDF
The authors introduce the SMTp architecture - an SMT processor augmented with a coherence protocol thread context that together with a standard integrated memory controller can enable the design of scalable cache-coherent hardware Distributed Shared Memory (DSM) machines from commodity nodes. They describe the minor changes needed to a conventional out-of-order multithreaded core to realize SMTp, discussing issues related to both deadlock avoidance and performance. They then compare SMTp performance to that of various conventional DSM machines with normal SMT processors both with and without integrated memory controllers.

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