Sobel Edge Detection Using Parallel Architecture Based on FPGA
In this paper, the authors propose an FPGA based approach known as Sobel Edge Detection (SED). RGB image is taken by the computer source and converted into binary image using Matlab. The proposed SED is modeled using parallel architecture and implemented in Verilog HDL. The whole process is performed in the hardware level that utilizes the resources of Xilinx ISE 12.4. The result shows good performance of edge detection with maximum frequency of 200MHz. The time from image read to final edge determined image would vary with the image size.