Soft-Edge Flip-flops for Improved Timing Yield: Design and Optimization
Parameter variations cause high yield losses due to their large impact on circuit delay. In this paper, the authors propose the use of so-called soft-edge flip-flops as an effective way to mitigate these yield losses. Soft-edge flip-flops have a small window of transparency (ranging from 0.25-3 FO4) instead of a hard edge, allowing limited cycle stealing on critical paths, and thus compensating for delay variations. By enabling time borrowing, soft-edge flip-flops allow random delay variations to average out across multiple logic stages.