Soft Error-Aware Design Optimization of Low Power and Time-Constrained Embedded Systems

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Provided by: edaa
Topic: Hardware
Format: PDF
In this paper, the authors examine the impact of application task mapping on the reliability of MPSoC in the presence of Single-Event Upsets (SEUs). They propose a novel soft error-aware design optimization using joint power minimization with voltage scaling and reliability improvement through application task mapping. The aim is to minimize the number of SEUs experienced by the MPSoC for a suitably identified voltage scaling of the system processing cores such that the power is reduced and the specified real-time constraint is met.
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