National Science Foundation
As the circuit feature size decreases, soft errors become an important issue for designing logic cells and memories. Quasi-Delay-Insensitive (QDI) circuits are the family of asynchronous circuits that operate with the weakest timing assumption (isochronic fork). This paper addresses the issue of soft errors in Quasi Delay-Insensitive (QDI) FPGA (Field-Programmable Gate Array). The authors combine two soft error mitigation schemes. One is to duplicate and double-check computation cells, and the other is to interlock coupled inverters of programmable bits. They present a soft-error tolerant logic cells of QDI FPGAs based on the schemes.