International Journal of Emerging Technology and Advanced Engineering (IJETAE)
The protection of processor-based systems to mitigate the harmful effect of transient faults. This paper proposes an Depth packet inspection methodology for facilitating the design of fault tolerant embedded systems, the packet inspection is possible in compressed data and thereby achieve high fault coverage in accuracy and speed. The methodology is supported by an infrastructure that hardware and software soft errors mitigation techniques in order to best satisfy both usual design constraints permits to easily combine hardware and software dependability requirements. It is based on a FPGA architecture that facilitates the implementation of software-based techniques, providing a uniform isolated from target hardening core that allows the automatic generation of protected source code.