Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing

Provided by: edaa
Topic: Hardware
Format: PDF
The High Efficiency Video Coding (HEVC) standard aims at providing 50% better compression compared to its predecessor at the cost of high computational complexity. To enable HEVC video encoding in real-time scenarios, special coding support for parallelization is provided in HEVC that can be exploited by many-core systems. In this paper, the authors present a HEVC software architecture where a video frame is adaptively divided into independent video frame regions which are processed concurrently on multiple cores. By balancing the workload of each video tile mapped to a particular core, the total power consumption of a system is reduced under a given frame-rate constraint.

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