Provided by: Association for Computing Machinery
Date Added: Mar 2007
Power estimation of microprocessors is mostly based on the internal information on the processor architecture such as activation/deactivation of each modules in the pipeline stages which is known via simulation or runtime counters. This paper presents a scheme for deriving a model for the power consumption of o-the-shelf RISC processors where such de-tailed internal information is not available. The proposed power model called IPI (Inter-Prefetch Interval) power model is based only on the processor I/O signals (i.e., memory access) which can be obtained for any microprocessor through external measurement.