Space Sensitive Cache Dumping for Post-silicon Validation

Provided by: edaa
Topic: Hardware
Format: PDF
The internal state of complex modern processors often needs to be dumped out frequently during post-silicon validation. Since the last level cache (considered L2 in this paper) holds most of the state, the volume of data dumped and the transfer time are dominated by the L2 cache. The limited bandwidth to transfer data off-chip coupled with the large size of L2 cache results in stalling the processor for long durations when dumping the cache contents off-chip. To alleviate this, the authors propose to transfer only those cache lines that were updated since the previous dump.

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