Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression
VLSI technology scaling has introduced increased variations in VLSI designs, including variations in the VLSI manufacturing process, e.g., of layout geometry, dopant concentration, and stress and variations at system runtime, e.g., of temperature and power/ground supply voltage. Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, for which foundry confidentiality policy has largely been blamed. A significant part of process variations are design specific, and can only be extracted from production chip performance statistics.