Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures

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Provided by: Institute of Electrical & Electronic Engineers
Topic: Data Management
Format: PDF
In this paper, the authors propose a novel technique to alleviate the cost of timing error recovery, building upon the lockstep execution of Single-Instruction-Multiple-Data (SIMD) architectures. To support spatial memoization at the instruction level, they propose a Single-Strong-lane-Multiple-Weak-lane (SSMW) architecture. Spatial memoization exploits the value locality inside parallel programs, memoizes the result of an error-free execution of an instruction on the SS lane, and concurrently reuses the result to spatially correct errant instructions across MW lanes.
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