Speed Enhancement in 64 - Bit Parallel Prefix VLSI Adder Using an Efficient Method
High speed computation is an important parameter to evaluate the overall performance of computing devices. To manipulate the addition operations with more speed and accuracy parallel prefix addition is a better method. In this paper a 64-bit parallel prefix addition is implemented with the help of cells like black cell and grey cell for carry generation and propagation. This process will gives high speed computations with high fan-out and makes carry operations easier. Xilinx 14.5 vivado tool has been used for the simulation of proposed 64-bit adder.