Provided by: University of Peloponnese
Date Added: Nov 2010
Spatial processing of sparse, irregular floating-point computation using a single FPGA enables up to an order of magnitude speedup (mean 2.8x speedup) over a conventional microprocessor for the SPICE circuit simulator. The authors decompose SPICE into its three constituent phases: model-evaluation, sparse matrix-solve, and iteration control and parallelize each phase independently. They exploit data-parallel device evaluations in the model-evaluation phase, sparse dataflow parallelism in the sparse matrix-solve phase and compose the complete design including the iteration control phase in a streaming fashion.