Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture

Provided by: Institute of Electrical & Electronic Engineers
Topic: Hardware
Format: PDF
A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed split-row method makes column processing parallelism easier to exploit, doubles available row processor parallelism, and significantly simplifies row processors - which results in smaller area, higher speeds, and lower energy dissipation. Simulation results over an additive white Gaussian channel show that the error performance of high row-weight codes with split-row decoding is within 0.3 - 0.6 dB of the min-sum and sum-product decoding algorithms.

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