Spurious Power Suppression Technique for VLSI Architecture

Provided by: Creative Commons
Topic: Hardware
Format: PDF
Using Spurious Power Suppression Technique (SPST) in VLSI will reduce the power consumption of the system significantly. Here, the authors are going to implement this design in Infinite Impulse Response (IIR) and Finite Impulse Response (FIR) filter architecture. When they are using this technique in these multipliers the no of partial products generated will be reduced to half which reduces the computation .Then obviously the power consumption is also reduced by this method using the Spartan 2 hardware device.

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