SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Provided by: Institute of Electrical & Electronic Engineers
Topic: Storage
Format: PDF
Reducing Static Random-Access Memory (SRAM) operational voltage can greatly improve energy efficiency, yet SRAM Vmin does not scale with technology due to increased process variability. Assist techniques have been shown to improve the operation of SRAM, but previous investigations of assist techniques at design time have either relied on static metrics that do not account for important transient effects or make specific assumptions about failure distributions. This paper uses importance sampling of dynamic failure metrics to quantify and analyze the effect of different assist techniques, array organization, and timing on Vmin at design time.

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